Modern integrated circuits are made up of literally millions of active devices such as transistors and capacitors. These devices are initially isolated from one another but are later interconnected together to form functional circuits. Typical interconnection structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. The quality of the interconnection structure drastically affects the performance and reliability of the fabricated circuit. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits.
FIG. 1 is a cross-sectional illustration of a conventional interconnection structure used in the semiconductor industry. Metal lines 104 and 106, which are typically formed of copper, aluminum, or alloys thereof, are used to couple active devices (not shown) into functional circuits. A dielectric layer 108 electrically isolates an upper metallization layer and a lower metallization layer. Electrical connections between metallization layers are made between metal lines 104 and 106 through metal vias 110 and 112.
The pitch P in the upper metallization layer, which includes metal lines 104 and 106 is the sum of the metal line width W and line spacing S. Typically, the vias 110 and 112 have a width R of between about 0.45 P and about 0.5 P, the line spacing S is between about 0.4 P and about 0.5 P, and the line width W is between about 0.5 P and about 0.6 P. Therefore, in a typical interconnection design scheme, line spacing S is about one half of the pitch or slightly less.
The interconnection structure of FIG. 1 suffers drawbacks, however. As the existing back end of line (BEOL) design rules require a decreasing pitch P for laying out metal lines in interconnection structures, the line spacing S becomes very small also. This causes the parasitic capacitance between interconnection lines 104 and 106 to be high. As a result, the RC delay of the integrated circuits increases. Additionally, with a smaller spacing S between the metal lines, leakage current may become significant.
An article by Viet H. Nguyen, et al., entitled “An Analysis of the Effect of Wire Resistance on Circuit Level Performance at the 45-nm Technology Node,” has pointed out that parasitic capacitance has a much larger impact on RC delay than does line resistance for most of the random logic circuits with a local interconnect length of less than about 1000 μm, and even more particularly less than about 500 μm. When the interconnection lines are longer than about 1000 μm, the line resistance starts to dominate the RC delay.
Further research has revealed that in typical low BEOL loading products, for example, communication chips, about 70 to 80 percent of the lengths of the interconnection lines are 500 μm or less. Therefore, by reducing parasitic capacitances, the RC delays on about 70 to 80 percent of the interconnection lines can be noticeably improved.
One way to reduce parasitic capacitance is to lower the dielectric constant of the inter-metal dielectric layer 108. However, the k value of the inter-metal dielectric layer 108 has typically already been lowered to what existing technology allows. Besides, lowering the k value of inter-metal dielectric layer 108 is accompanied by the side effects of weaker mechanical properties and higher vulnerability to the “poisoning” of process chemicals.
Therefore, what is needed is a novel interconnection structure design so that RC delay and leakage currents are reduced without compromising other characteristics of the integrated circuits.